Engineers at Massachusetts Institute of Technology developed a process for creating nanoscale transistors, like those designed for computer logic operations, made of indium gallium arsenide. The team from MIT’s Microsystems Technology Laboratories will discuss its findings later this week at the International Electron Devices Meeting in San Francisco.
The team led by electrical engineering professor and lab director Jesús del Alamo (pictured left) aimed to extend the limits of Moore’s Law — the prediction by Gordon Moore, founder of chip maker Intel, that the number of transistors on microchips will double every two years. That expectation, as well as demand for increasingly smaller, faster, and smarter electronics, keeps the pressure on industry for chips with more power, yet in a smaller size.
A major constraint in meeting this demand is the ability of silicon to support sufficient power for more transistors, particularly when chips are reduced to nanoscale size (where 1 nanometer equals 1 billionth of a meter). One material capable of replacing silicon is indium gallium arsenide, an alloy of gallium arsenide and indium arsenide, which has proven superior electrical properties and is found today in fiber-optic communication and radar technologies.
The problem keeping chip manufacturers from using this material is the lack of a technique to produce devices small enough to be packed in nanoscale indium gallium arsenide chips. The MIT team, including graduate student Jianqian Lin and engineering professor Dimitri Antoniadis, devised a process to build a metal-oxide semiconductor field-effect transistor or MOSFET device with indium gallium arsenide only 22 nanometers long.
MOSFETs are chips designed for common computer logic operations. The transistor has three electrodes: a source, drain, and gate that controls the flow of electrons between the other two. Because the extremely small space, the three electrodes must be placed in tight proximity, requiring a level of precision impossible for today’s chip tools to achieve. Instead, the MIT team devised a method that allows the gate to align itself between the source and drain.
That process starts by growing a thin layer of indium gallium arsenide with molecular beam epitaxy, a semiconductor industry technique where evaporated atoms of indium, gallium, and arsenic react with each other within a vacuum to form a single-crystal compound of the material. The next step applies a layer of molybdenum as the source and drain contact metal.
Electron beam lithography, another semiconductor technique, is used next to draw a fine pattern on the substrate with a tiny electron beam, after which the unwanted indium gallium arsenide is etched away and the gate oxide is deposited in the gap between the source and drain. Evaporated molybdenum is then aimed at the gap on the device surface, where it forms the gate between the two other electrodes. “Through a combination of etching and deposition,” says del Alamo, “we can get the gate nestled [between the electrodes] with tiny gaps around it.”
The next steps in the project are expected to improve the speed and performance of the indium gallium arsenide chip, by eliminating unwanted resistance in the device. Once that goal is achieved, the team plans to reduce the size of the device further, to 10 nanometers or less.
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