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Nanotech Fabrication Process Developed for Smaller Chips

H.-S. Philip Wong (Stanford University)

H.-S. Philip Wong (Stanford University)

Engineers at Stanford University and two Silicon Valley companies in California have devised a method of creating contact hole patterns for semiconductors that can reduce the size of logic and memory chips, while maintaining their fabrication accuracy. The findings of the team led by Stanford engineering professor H.-S. Philip Wong (pictured left) appear online in the journal Advanced Materials; paid subscription required.

The research was funded by Semiconductor Research Corporation in Research Triangle Park, North Carolina and National Science Foundation.

Wong and colleagues used a process called directed self-assembly (DSA) where a block copolymer or polymer blend is deposited on a wafer substrate. A block copolymer is a polymer chemical made of multiple sequences of the same monomer, called blocks, alternating in series with different monomer blocks. The materials are then subjected to heat for hardening, and this annealing process causes the material to form ordered structures.

The team, which includes participants from Applied Materials Inc. in Sunnyvale and Xilinx Inc. in San Jose, applied a block copolymer film to a wafer. The researchers then used common chip lithography techniques to etch impressions into the wafer surface. These impressions produce a pattern of irregularly placed indentations that serve as templates to guide the movement of molecules of the block copolymer into self-assembled configurations.

Wong and colleagues varied the size and shape of the guiding templates to space holes more closely than current lithographic methods permit. The closely packed patterns that emerged, say the researchers, enable the semiconductor industry to build smaller, faster, and more energy efficient chips than provided by larger devices.

By applying this combination of chemical and thermal processes to create their DSA method for making circuits at 22 nanometers, the research team believes that this fabrication technique will enable pattern etching for next-generation chips down to an even smaller 14 nanometers (1 nanometer equals 1 billionth of a meter). The team also used polyethylene glycol monomethyl ether acetate as a solvent in the coating and etching steps, which they say is safer than most solvents now used in chip fabrication.

“This irregular solution for DSA,” says Wong, “also allows you to heal imperfections in the pattern and maintain higher resolution and finer features on the wafer than by any other viable alternative.” Wong adds that the team applied this process to standard cell libraries of very large-scale integration (VLSI) chips. “The result is a composed pattern of real circuits, not just test structures,” Wong notes.

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